1. Field of the Invention
This invention generally relates to non-volatile electrically alterable semiconductor memory devices having split gate structures and to a method of fabricating such devices.
2. Description of the Related Art
Numerous electrically alterable non-volatile semiconductor memory devices such as EEPROMS (electrically erasable programmable read-only-memory) have been developed in recent years. Particularly, flash EEPROMs have received considerable attention, and are hereinafter referred to as flash memories.
In contrast to prior EEPROMS which have additional gating devices for each cell and are erased by one memory bit, rapid advancements in the high integration of flash memory devices has been accomplished by erasing by a predetermined unit. The unit is either a predetermined portion of the integrated device, which is hereinafter referred to as a `block`, or the entire portion of a memory device. This unit tends to be larger in size with the increase in integration.
Since flash memory devices have been regarded until recently to be used interchangeably with ultra-violet light erasable EPROMs, the unit size for the erase operation has not been of primary concern. However, as the application field of the flash memory expands it has become more desirable for the memory device to have a unit for the erasing operation which is adjustable in size.
A flash memory device is disclosed in U.S. Pat. No. 5,280,446, wherein a high device integration has been achieved by use of embedded diffusion layers for connecting a plurality of memory cells. However, since memory bit lines are formed with diffusion layers having relatively large capacitance in the memory circuit construction, this degrades the readout speed performance, which becomes more pronounced for mass storage devices.
The CR (capacitance/resistance) delay is known as one of the primary factors effecting the access time to memory cells, and capacitance C and resistance R of this structure of the embedded layer type device are determined by the configuration of diffusion bit lines (source and drain diffusion strips) and polysilicon word lines in the structure.
To reduce the CR delay, a plurality of contact holes are formed to be connected to bit lines and word lines, and metal strips are further provided in the disclosure. Although a reduction in circuit resistance is achieved by connecting these lines to the metal strips to thereby reduce the CR delay, at least two layers of metal strips are required, as disclosed therein.
FIG. 1 is a top view of a prior art memory cell having a split-gate structure.
A source diffusion strip 109 and a drain diffusion strip 108 are formed in a semiconductor substrate in the bit line direction. A control gate strip 105 is formed between the source and drain strips, and adjacent to the drain strip. That is to say, the control gate strip 105 is formed closer to the drain strip than to the source strip. A select gate strip 106 is also formed in the word line direction, which is perpendicular to the direction of the bit line and the control gate strip 105.
A portion of a memory channel 102, which is defined between the source and drain strips and adjacent to the drain region, is formed underneath the control gate strip 105 having an underlying floating gate. The remainder 101 of the memory channel is formed underneath the select gate strip 106 and between the memory channel 102, and the source strip 109 to be a channel of a select transistor. In addition, a plurality of the channel portions 101 and 102 are separated and isolated electrically from other channel portions in the bit line direction by field oxide regions 107 formed in between in a rectangular shape.
Semiconductor memory devices are fabricated, in general, with the minimum dimension feasible by the fabrication process. For memory devices such as those shown in FIG. 1, therefore, the minimum dimension for one memory cell in the word line direction 103 is generally larger than that in the bit line direction 104 because of the two channel portions compared to one portion for the latter direction.
Referring to FIG. 2, there is shown a top view of diffusion strips and their fields in a memory array structure. A plurality of source diffusion and drain diffusion strips 121 and 122, respectively, are alternatively formed, and channel regions 125 are also formed in between to thereby consist of memory cells. Also, a plurality of the field oxide regions 124 are formed for isolating memory cells in the bit line direction.
On every other strip of the source and drain diffusions 121 and 122, a plurality of contact holes 123 are formed, through which connections to overlying metal bit lines are to be made, thereby decreasing bit line resistance. By forming contact holes also on both end portions of the select gate strips and by connecting to overlying metal word lines (not shown), word line resistance also decreases.
Referring to FIG. 3, a cross sectional view of a prior art memory device is illustrated in the bit line direction (the column direction in FIG. 2), wherein an interlayer dielectrics 134 is formed between polysilicon and metal layers. The interlayer dielectric 134 isolates or insulates the floating gates 130, control gates 105 and select gates 106 from each other.
As illustrated also in FIG. 3, memory regions 131 are each formed including a plurality of memory transistors, and contact holes 132 are each formed between the memory regions for connection to the source and drain regions of the memory cells. Furthermore, there are also shown transistor gates 135 of, and contact holes 133 for, surrounding circuit components.
The memory cell region 131 consists of three layers of polysilicon, as illustrated in FIG. 3, thereby giving rise to a level difference which is larger when compared to that in the immediately surrounding regions which consist of only one polysilicon layer. Therefore, contact holes 132 formed in the vicinity of the memory regions 131 are higher than those in the immediately surrounding regions.
Because of a limitation in the focal depth feasible during the photolithography process, the above-mentioned level difference in the memory regions reduces the spatial resolution during the process, thereby causing unwanted increase in the minimum dimension for the fabrication.
The diameter of through-holes is generally larger than that of contact holes during process steps. When metal bit lines are formed over the metal word lines, a through hole 141 has to be formed on top of a contact hole in the memory region as illustrated in FIG. 4, and this results in the pitch of metal bit lines exceeded by that of through-holes. Accordingly, when a contact hole has already been fabricated with the minimum fabrication dimension in the source and drain regions, it is not feasible to form a through-hole on top of a contact hole and metal bit lines have to be formed below the metal word lines.
Referring now to FIG. 5, a cross sectional view of a prior art memory device is illustrated in the bit line direction, wherein a first metal layer (a lowermost metal layer in case of a plurality metal layers) is used as metal bit lines, while a second metal layer (a second lowermost metal layer in case of a plurality metal layers) is used as metal word lines.
Since the pitch of the memory cell in the bit line direction 104 is smaller than that in the word line direction 103, as illustrated earlier in FIG. 1, there results in the construction of FIG. 5, wherein the pitch of the second metal layer 151 is larger compared to the pitch of the memory cells 104 in the bit line direction.
The block unit for an erase operation has generally been determined by the way the memory bit lines are shared. As aforementioned, this gives rise to the limitations of prior art memory devices, among others, in that all of the memory cells sharing one single memory bit line are generally erased and the size of the erase block has not been selected at will.
In addition, for the prior art flash memory devices, difficulties have been experienced in erasure by ultra-violet light exposure, which is requisite for preparing reference cells in memory cell arrays. These reference cells are considerably important for implementing standard signal generation for readout circuits and process data analysis.
This erasure is carried out for memory cells to release electric charges remaining in the floating gate after finishing of the fabrication process steps. After the charges are released, a group of memory cells can be used as reference cells.
In the prior art memory devices, wherein the pitch of an overlying metal layer is different from the pitch of memory cells disposed below the metal lines, and wherein an ultra violet light erasure may not be achieved for the entire array of cells due to shaded memory cells which are caused by the above-mentioned difference between the pitches. These non-erased cells will result in every certain number of cells in the bit line direction.
In addition, when the first or the lowermost metal layer is used as metal bit lines, a relatively small distance results between select gates, thereby giving rise to the increase in CR delay of the circuit.